The present invention relates to integrated circuits and more particularly to an integrated circuit having a built-in self test design.
The ease with which an integrated circuit can be tested is dependent on the controllability and observability of each of its components. A number of testing techniques have previously been proposed which have as their objective the increase in the controllability and observability of each of the components in the integrated circuit. The proposed techniques fall broadly into two groups known respectively as "ad hoc" and "structured" testing methods.
One "ad hoc" method involves the addition of extra test points to the integrated circuit. By means of suitable computer programs it is possible to calculate the number and sequence of test signals to the inputs necessary to test each gate in the circuit as well as determining the best positions to insert test points. A practical implementation however on a chip may involve the use of numerous multiplexers to ease the external connection problem.
Another "ad-hoc" method is "partitioning", where the circuit is broken down into a number of more manageable blocks. These blocks are then connected to the input and output pins to facilitate the testing of each block individually. Problems arise with this method when it is desired to test components of very large scale integrated circuits as design difficulties may arise when attempting to choose and gain access to the partitions.
In the case of "structured" testing methods, the testability measures form an active part of the system design. An example in this field has been the "Scan Path" and "LSSD" (Level Sensitive Scan Design) techniques, where a "scan mode" input configures all the register elements in a chip together to form a long shift register. By adding, "scan in" and "scan out" pins, the complete state of the chip can be determined or defined.
To use the scan path technique, a typical sequence would involve first "scanning in" a specific state. One or more clock pulses would then be applied while the circuit is in "normal" mode to actually test its operation. The next "starting state" would then be "scanned in" as the resulting state was being "scanned out" and checked against the expected result.
The main problem with this technique is that it is generally necessary to set up the initial conditions for a large number of tests. Whereas the test itself may only take one clock cycle, in order to "scan in" an initial state, and/or "scan out" a result may take as many clock cycles as there are registers in the whole circuit. Since it is necessary to stop the normal operation while internal states are being scanned in or out, continuous real-time testing is not possible. Furthermore expensive test equipment is still required to provide predetermined test patterns to the inputs of the circuit.
The LSSD variation involves the use of "level sensitive" registers which appear transparent for one particular clock level. Two such registers and a two phase clock are necessary to implement the scan path shift register.
Proposals have also been made previously for the self-testing of integrated circuits. One of these techniques, described later with reference to FIGS. 1 and 2 of the accompanying drawings, is known as Built-In Logic Block Observation (BILBO) and by using BILBO registers incorporates the concepts of both the Scan Path described above and the concept of a Signature Analysis technique. The BILBO registers are used to test a combinatorial logic circuit by which is meant a circuit whose output signals are always the same for the same combination of input signals. Such tests can be performed at full speed.
BILBO registers have also been used to test circuits that include internal registers. The internal registers form a Scan-path which is loaded with pseudo-random patterns by means of a BILBO register on the Scan-Path input. As with the normal Scan-Path techiniques, the circuit is then switched into normal operation for one or more clock cycles. The resulting state is then scanned into a further BILBO register which computes a Signature from the serial stream of data from the Scan-path as a new pseudo-random state is being scanned in. This technique retains the problems of long test times characteristic of normal scan path techniques, because the complete state of an integrated circuit must still be scanned out and a new state scanned in a very large number of times for a thorough test to be carried out. Self-testing circuitry has been proposed in European Patent Application Nos. 0108255 and 0108256. The circuitry described employs register elements operable in the conventional modes of "normal operation" and "scan path" (LSSD type) as well as a "self test" mode in which they perform a signature analysis upon the output of combinatorial logic that feeds the register elements.
European Patent Application No. 0108256 teaches circuitry in which during operation each register element on a chip supplies test patterns to "down-stream" logic simultaneously as performing a signature analysis upon the output from "up-stream" logic. European Patent Application No. 0108255 teaches circuitry in which a plurality of such chips are used to form a larger system with built-in test facilities. To this end, a separate pseudo random test pattern generator and a separate signature analyser are added to the system to respectively generate the first pseudo-random patterns (at the start of the scan path) and analyse the signals (at the end of the scan path) of each of the component chips. Additional test control circuitry is also required to perform a test on the system.
The register elements in a particular chip in the circuitry described in European patent application Nos. 0108256 and 0108255 are always operated in the same mode as each other. Thus signature analysis data from "up-stream" logic is used as test pattern data to "down-stream" logic. It would be necessary therefore to run expensive computer simulation programs to test the fault coverage. If the fault coverage is found to be unacceptably low then the only recourse would be to redesign the circuit. It would then be necessary to repeat the computer simulation process to ascertain whether or not the fault coverage had been improved. Furthermore, the need for external equipment both to control the test and to check the output during the test is extremely expensive.
The present invention strives to provide integrated circuits (which may include many internal registers) with a built-in self test facility where the self test can be designed to be completed within any reasonable given time and still guarantee a very high fault coverage without the necessity for fault simulation.